1. Field of the Invention
The present invention relates to a display driving circuit, and more particularly, to a display driving circuit which can reduce power consumption.
2. Description of the Related Art
In general, a display driving IC adopts an alternate current driving scheme in order to prevent an image sticking phenomenon that can occur due to the fact that various ionic or polar substances present in a display adhere to electrodes. Also, a flicker phenomenon can occur due to the parasitic capacitance of TFTs (thin film transistors) disposed in a display panel. Thus, in order to control the flicker phenomenon, an inversion driving method has been proposed in the art.
The inversion driving method is generally divided into frame inversion, line inversion and dot inversion methods.
FIG. 1 is a view explaining a frame inversion method.
FIG. 2 is a view explaining a line inversion method.
FIG. 3 is a view explaining a dot inversion method.
Referring to FIG. 1, in the frame inversion method, inversion is implemented every time when one frame (Nth frame) is changed to another frame ((N+1)th frame). In these drawings, + and − represent different polarities. Referring to FIG. 2, in the line inversion method, inversion is implemented by the unit of a line. The drawing shows inversion by the unit of a vertical line. Referring to FIG. 3, in the dot inversion method, inversion is implemented by the unit of pixel. The dot inversion method can be divided into a first method in which inversion is implemented by the unit of one-dot pixel and a second method in which inversion is implemented by the unit of two-dot pixel as a group.
While the frame inversion method shown in FIG. 1 is susceptible to the flicker phenomenon due to non-symmetry in the transmittance of a first polarity (+) and a second polarity (−) and is vulnerable to cross-talk due to interference between data, it provides advantages in that current consumption is small.
The line inversion method shown in FIG. 2 compensates for the luminance deviation between adjoining lines due to the voltages of the opposite polarities applied to the lines, using a spatial averaging technique, whereby the flicker phenomenon and the cross-talk between the lines can be reduced compared to the frame inversion method. However, in the line inversion method, since the frequency of alternate current increases compared to the frame inversion method, disadvantages are caused in that current consumption relatively increases.
The dot inversion method shown in FIG. 3 can reduce the flicker phenomenon by using the spatial averaging technique, whereas it has disadvantages in that current consumption is most large since the frequency of alternate current is greater than the two above-described methods. Nevertheless, because the dot inversion method provides advantages in that the flicker phenomenon is minimized, it is adopted most frequently. The following description will be given with regard to a display driving circuit which adopts the dot inversion method.
FIG. 4 is a view illustrating a portion of an output part of a display driving circuit.
Referring to FIG. 4, a conventional display driving circuit 400 includes a buffer section 410, an N-dot switch circuit 420, and a charge sharing switch circuit 430. The buffer section 410 has a plurality of buffers 411 through 416 which buffer M (M is an integer) number of pixel driving signals D1 through DM outputted from a plurality of DACs (digital-to-analog converters) (not shown). The N-dot switch circuit 420 selects the paths of the plurality of pixel driving signals D1 through DM outputted from the buffer section 410, depending upon the value of an N (N is an integer). The charge sharing switch circuit 430 shares charges between a plurality of output terminals output#1 through output#M for outputting the signals outputted from the N-dot switch circuit 420. The signals outputted from the plurality of output terminals output#1 through output#M drive respective pixels (not shown) which constitute a display panel.
When the case, in which the respective data D1 through DM outputted from the DACs are outputted through the corresponding output terminals output#1 through output#M via corresponding first path selecting switches S1, is called normal data transmission, the case, in which the respective data D1 through DM outputted from the DACs are outputted through the corresponding output terminals output#1 through output#M cross-connected to corresponding second path selecting switches S2, can be called inverted data transmission. This is because, in the phases of the data D1 through DM consecutively outputted from the DACs, for example, when the odd data D1, D3, . . . have a positive (+) phase, the even data D2, D4, . . . have a negative (−) phase.
FIG. 5 is an internal waveform diagram of the display driving circuit.
The waveform diagram shown in FIG. 5 has been taken on the basis of a vertical line in the two-dot inversion method shown in FIG. 3. Therefore, when viewing the waveform diagram in terms of time, in load signal Load, a first enabled signal is for the pixels included in a first line, and a second enabled signal is for the pixels includes in a second line. Since the waveform diagram has been taken on the basis of a vertical line, referring to FIG. 3, two data having an optional polarity are consecutively outputted, and then, two data having a polarity opposite to the optional polarity are consecutively outputted.
The way of inversion is determined by a POL signal POL and the load signal Load. In this regard, since one POL signal POL corresponds to two load signals Load, FIG. 5 corresponds to a waveform diagram for the two-dot inversion method. The POL signal POL and the load signal Load are signals generally used in a display driving circuit, and function to control a line register for storing data and a panel driving IC for generating a signal for driving a panel, using an analog voltage corresponding to the data outputted from the line register.
When the POL signal POL is in a logic high state, in the outputs ‘Even Channel’ supplied to optional even pixels included in an optional horizontal line, two data of a first polarity (+) are consecutively outputted in response to load signals Load, and in the outputs ‘Odd Channel’ supplied to odd pixels included in the same horizontal line, two data of a second polarity (−) are consecutively outputted in response to load signals Load. When the POL signal POL is in a logic low state, in the outputs ‘Odd Channel’ supplied to optional odd pixels, two data of the first polarity (+) are consecutively outputted in response to load signals Load, and in the outputs ‘Even Channel’ supplied to even pixels, two data of the second polarity (−) are consecutively outputted in response to load signals Load.
A first path selecting signal SW1 applied to the first path selecting switches S1 has the same phase as the POL signal POL, and a second path selecting signal SW2 applied to the second path selecting switches S2 has a phase opposite to that of the POL signal POL. In the case of the output signals ‘Even Channel’ supplied to optional even pixels, when the phase of the POL signal POL is logic high, the outputs of the plurality of buffers constituting the buffer section 410 are outputted as final outputs by the first path selecting switches S1 which are turned on in response to the first path selecting signal SW1.
In the conventional art, in order to reduce current consumption, a charge sharing control signal SW3 to be applied to charge sharing control switches S3 connecting adjoining column data output terminals is enabled so that adjoining column data outputs can share charges through a portion of the interval of the load signal Load. At this time, a voltage change does not occur from the first polarity (+) to the second polarity (−) or vice versa as a transition to a different polarity, but a voltage change occurs from a middle voltage level CSM as a middle point between the first polarity and the second polarity to the first polarity (+) or from the CSM to the second polarity (−), whereby an amount of current consumption can be reduced.
Nonetheless, in the charge sharing interval in which the charge sharing control signal SW3 is enabled, the transition from the first polarity (+) to the middle voltage level CSM and the transition from the second polarity (−) to the middle voltage level CSM require a substantial amount of current consumption, by which a drawback is caused. This is because voltage level differences between the first polarity (+) and the middle voltage level CSM and between the second polarity (−) and the middle voltage level CSM are still substantial.